1. Field of the Invention
The invention relates generally to the field of data processing systems and concerns the execution of instructions on multibyte data strings. More particularly, the invention relates to a hardware data string operation controller (also referred to herein as a hardware "sequencer"), which is capable of manipulating data in main storage by processing certain left to right instructions (i.e., instructions that are processed from a first memory address to a higher second memory address), or right to left instructions (i.e., instructions that are processed from a first memory address to a lower second memory address), having variable length operands, under the control of a single control word.
2. Description of the Related Art
Main store string operations are well known and can be used in computer systems, such as the IBM System 370, to transfer data from one main store memory location to another. These operations may alter the data being transferred in conjunction with performing certain arithmetic logic unit (ALU) operations (for example, an "ADD", or similar two operand operation), or the data being transferred can be moved unchanged (for example, via a "MOVE" type operation).
Additionally, well known operations exist that compare two data strings without storing any result back to main store (for example, an instruction that tests for 0 on the difference between two operands).
The length of data strings serviced by the aforementioned types of operations can vary from one byte to hundreds of bytes.
A typical instruction processing sequence (in a system like the IBM System 370) would entail fetching an instruction from main store; decoding the instruction; translating the virtual address of the operand(s) associated with the instruction to a main store address(es); and then performing the operation specified by the fetched instruction on the operand(s).
A fault signal is typically generated if the translation indicates a main store address does not exist for one or more operands.
Assuming no fault, it is well known in the prior art to perform the aforementioned data string operations (upon the operands associated with a given instruction), by using microcode driven hardware. This hardware, in conjunction with the microcode, actually performs the function designated by the given instruction.
The hardware controls of a microprogram controlled computer are mainly data gates that route data into and out of registers, counters, adders, and so on. It is typical in such systems for one instruction (program instruction, microcode, microdeinstruction, or control word) to provide the data gates and controls for one machine cycle.
A simple and well known technique for performing data string operations, is to use a microprocessor controlled computer to execute one control word for each byte of data being processed within a string. Using this technique, to for example add the contents of a first doubleword (8 bytes) to a second doubleword, would require a minimum of 8 machine cycles (plus overhead for fetching the data, storing the results, etc.). Such techniques are unacceptably slow when measured against the speed of other present day processor components (such as cache memory) which interface with the string processing mechanism.
Another example of a prior art technique for performing data string operations is taught in copending U.S Pat. application Ser. No. 07/121,443, filed on Nov. 17, 1987, now U.S. Pat. No. 4,933,849 issued on Jun. 12, 1990, assigned to the same assignee as the present invention. This copending patent application, entitled "Microcode Branch Based Upon Operand Length and Alignment", is hereby incorporated by reference.
The incorporated copending patent application (sometimes referred to hereinafter as the "Microcode Branch" invention), teaches a hardware assist running under horizontal microcode. The Microcode Branch invention operates by branching to one of a plurality of microcode subroutines (which actually perform the data manipulation), based upon the alignment of the data strings being processed and number of bytes to be operated on.
In particular, the branching technique taught requires: (1) a determination of operand byte alignment (alignment within registers into which the operands are fetched from main store); (2) a determination of the number of operand bytes remaining to be processed by a given instruction; and (3) a determination of which of a plurality of microinstruction (control word) subroutines should be called upon to perform the actual data manipulation, based at least in part, on the number of bytes of the operand remaining to be processed.
Utilizing the techniques taught in the incorporated copending patent application, a system's data flow paths can be more effectively used, particularly when compared with the byte by byte processing approach first referred to hereinabove.
However, the techniques taught in the incorporated reference are problematic in that they require the use of an excessive amount of control storage (to store the various subroutines) and require the expenditure of significant amounts of overhead to perform maintenance operations on string pointers and counters.
Furthermore, the techniques taught in the incorporated reference only relate to left to right instructions (e.g., "MOVE" instructions), and are not suitable for processing certain multibyte variable length right to left instructions (such as an "ADD").
Accordingly, it would be desirable if methods and apparatus could be provided which perform variable length main store string operations using only a single control word rather than the plurality of control words that are required by prior art string processing techniques.
Furthermore, it would be desirable to be able execute at least a subset of both right to left instructions and left to right instructions, having variable length multibyte operands, using the aforementioned desirable methods and apparatus.
Still further, it would be desirable to be able to perform multicycle storage to storage operations on variable length multibyte operand data, using only the single control word referred to hereinbefore.
Further yet, it would be desirable to be able to provide a hardware implementation of the desired methods and apparatus, which: (1) rapidly performs string processing by anticipating the need to fetch (and store) data (so as to be compatible with, and take advantage of, other high speed processor components); (2) minimizes control store requirements by eliminating the need to store the aforementioned plurality of microcode subroutines; and (3) reduces the processing time needed to perform multibyte variable length data string operations over one or more machine cycles by eliminating both the need to perform software branches, and the need to maintain certain string pointers and counters.